In a differential output circuit in which a signal of an integrated circuit is transmitted to another integrated circuit through a differential transmission line, it is a common practice to apply pre-emphasis with a loss of the transmission line took into account and to transmit the pre-emphasized signal. In the output circuit having a pre-emphasis function, the pre-emphasis is applied when current bit data to be output is changed from immediately preceding output bit data. When the current bit data does not change from the immediately preceding output bit data, the pre-emphasis is not applied.
In the differential output circuit having the pre-emphasis function, there may be a difference in a common mode voltage (VCM) between a transition bit and a de-emphasis bit (De-emphasis bit). The common mode voltage (VCM) is a center voltage of differential output signals. The transition bit is a bit which has transitioned from the value of the immediately preceding bit data and to which the pre-emphasis has been applied. The de-emphasis bit is a bit to which the pre-emphasis has not been applied. When the common mode voltage (VCM) greatly varies between the transition bit and the de-emphasis bit, non-conformity with specifications of a standard interface such as PCI-Express/Serial-ATA/CEI may occur. FIG. 11 shows an example of specifications for an AC common mode voltage (Vcmac: AC coupled common mode voltage) of the standard interface specifications. In the output circuit conforming to these standard interface specifications, operation with a low supply voltage is demanded so as to achieve low power consumption. When a large differential output amplitude (greater than or equal to 800 mV and less than or equal to 1200 mV) of the PCI-Express interface is to be achieved with the low supply voltage, the common mode voltage (VCM) tends to greatly vary due to the difference of the common mode voltage (VCM) between the transition bit and the de-emphasis bit. For this reason, the need for reduction or suppression of the variation of the common mode voltage (VCM) increases. Related arts of an output circuit having the pre-emphasis function (without a function of suppressing the variation of the VCM) and an output circuit having the function of suppressing the variation of the VCM will be described below.
FIG. 6 is a diagram showing a configuration of the output circuit having the pre-emphasis function (refer to Patent Document 1). Referring to FIG. 6, the output circuit includes a driver main buffer 10 and a pre-emphasis buffer 20. The driver main buffer 10 includes an NMOS transistor (current source transistor) N11 which has a source connected to a low-potential side power supply VSS, NMOS transistors N1 and N2 which have coupled sources connected to a drain of the current source transistor N11, have gates connected to differential input terminals INT and INB, respectively, and have drains connected to differential output terminals OUTB (also referred to as an negative-phase output terminal or an inverting output terminal) and OUTT (also referred to as a positive-phase output terminal or a non-inverting output terminal), respectively, and resistors R1 and R2 respectively connected between a high-potential side power supply VDD and the differential output terminals OUTB and OUTT (or the drains of the NMOS transistors N1 and N2). The NMOS transistor N11 has a gate supplied with a bias voltage BIAS.
The pre-emphasis buffer 20 includes an NMOS transistor (current source transistor) N12 has a source connected to the low-potential side power supply VSS and NMOS transistors N3 and N4 which have coupled sources connected to a drain of the current source transistor N12, have gates respectively connected to terminals EMT and EMB that differentially receive control signals (emphasis signals), and have drains respectively connected to the differential output terminals OUTB and OUTT. The NMOS transistor N12 has a gate supplied with the bias voltage BIAS. Reference characters T and B at the end of the name of a terminal or a signal such as OUTT, OUTB, EMT, EMB, and the like respectively indicate a positive phase (True) and a negative phase (Bar).
FIG. 7 is a timing chart for explaining the operation of the circuit in FIG. 6. The timing chart in FIG. 7 is newly prepared by the inventor of this application in order to explain the operation of the circuit in FIG. 6. FIG. 7 shows voltage waveforms of the terminals INT and INB, the terminals EMT and EMB, the terminal OUTB, a common mode voltage (VCM), the terminal OUTT, a drain node VS2 of the NMOS transistor N12 and a drain node VS1 of the NMOS transistor N11, and ON/OFF states of the NMOS transistors N1, N2, N3, and N4. Referring to FIG. 7, reference numerals (1) to (11) above the terminal INT respectively indicate timing periods. Details of the operation of the circuit in FIG. 6 will be described with reference to the timing chart in FIG. 7. In the following description, the name of a terminal may be commonly used as a signal name at the terminal.
<Period (1)>
The terminals (INT, INB) respectively transition to (High, Low) from (Low, High) levels immediately before the beginning of the timing chart. The terminals (EMT, EMB) are respectively kept (High, Low). In this period, the NMOS transistor N1 is turned ON, and the MOS transistor N2 is turned OFF. The NMOS transistor N3 is kept ON, and the NMOS transistor N4 is kept OFF. Then, differential output signals OUTT and OUTB assume a pre-emphasized High level (VOHP) and a pre-emphasized Low level (VOLP), respectively. The Low level of the output (VOLP: Voltage Output Low Pre-emphasized) in this case is low, and a voltage at a drain node VS1 of the current source transistor N11 and a voltage at a drain node VS2 of the current source transistor N12 are also low. That is, when signals (complementary signals) supplied to the differential input terminals (INT, INB) of the output circuit respectively change from (Low, High) to (High, Low), the terminals (EMT, EMB) are respectively set to (High, Low). Then, the terminals (OUTT, OUTB) are respectively set to the levels (VOHP, VOLP).
<Period (2)>
The terminals (INT, INB) are respectively kept (High, Low). The terminals (EMT, EMB) are respectively set to (Low, High). When the signals (complementary signals) supplied to the differential input terminals (INT, INB) of the output circuit are unchanged and remain (High, Low), the terminals (EMT, EMB) are respectively set to (Low, High). The output terminals OUTT and OUTB are respectively set to a level lower than an output voltage VOHP and a level higher than the output voltage VOLP, or de-emphasized levels. In the period (2), the NMOS transistor N1 is kept ON. However, the NMOS transistor N3 is turned OFF, and the NMOS transistor N4 is turned ON. The differential output signals (OUTT, OUTB) have de-emphasized waveforms. A Low potential of the output signal OUTB in the period (2) becomes higher than the voltage VOLP in the period (1) in which the NMOS transistors N1 and N3 are both turned on, because the NMOS transistor N3 is turned OFF in the period (2). A High potential of the output signal OUTT in the period (2) becomes lower than the voltage VOHP in the period (1) in which the NMOS transistors N2 and N4 are both turned off, because the NMOS transistor N4 is turned ON in the period (2). That is, at the pre-emphasis buffer 20, while the NMOS transistor N3 connected to the output terminal OUTB that outputs the Low output level VOLP is turned ON in the period (1), the NMOS transistor N4 connected to the output terminal OUTT that outputs the output level VOHP is turned ON in the period (2). For this reason, a level of the drain voltage VS2 at the current source transistor N12 rises from Va to Vb.
FIG. 8 shows a characteristic of a drain-to-source voltage Vds of the current source transistor N12 (plotted on an x axis) and a drain current Id (plotted on a y axis) in the pre-emphasis buffer of the circuit in FIG. 6. It can be seen from the Vds-Id characteristic in FIG. 8 that the drain current Id of the NMOS transistor N12 increases from Ia to Ib by an amount dI due to a rise of the voltage at the drain node VS2 of the current source transistor N12 from Va to Vb. For this reason, the common mode voltage (VCM) in the period (2) is lowered below the common mode voltage (VCM) in the period (1).
<Period (3)>
The terminals (INT, INB) are respectively set to (Low, High). The terminals (EMT, EMB) are respectively kept (Low, High). Since the terminal INT transitions from High to Low, pre-emphasis is performed with the terminal EMB kept High and the NMOS transistor N4 kept ON and with the terminal EMT kept Low and the NMOS transistor N3 kept OFF. Values at the terminals (EMT, EMB) are set to be the same as those in the period (2). The NMOS transistor N2 is turned ON, and the NMOS transistor N4 is kept ON. The NMOS transistor N1 is turned OFF, and the NMOS transistor N3 is kept OFF. Then, the differential output terminals OUTT and OUTB respectively assume the levels VOLP and VOHP, which are the pre-emphasized Low level and the pre-emphasized High level. The drain voltage VS1 of the current source transistor N11 and the drain voltage VS2 of the current source transistor N12 also are lowered.
<Period (4)>
The terminals (INT, INB) are respectively kept (Low, High). The terminals (EMT, EMB) are respectively set to (High, Low). The values at the terminals (EMT, EMB) are reversed from the states in the period (3). Thus, the NMOS transistor N4 is turned OFF, and the NMOS transistor N3 is turned ON. Then, the differential output terminals OUTT and OUTB assume the de-emphasized levels.
At the pre-emphasis buffer 20, while the NMOS transistor N4 connected to the output terminal OUTT that outputs the pre-emphasized Low level VOLP was ON in the period (3r), the NMOS transistor N3 connected to the output terminal OUTB that has output the pre-emphasized High level VOHD in the period (3) is turned ON in the period (4). For this reason, the voltage level of the drain node VS2 of the current source transistor N12 rises from Va to Vb. For the same reason as in the period (2), the drain current of the current source transistor N12 increases by the amount dI. The common mode voltage (VCM) in the period (4) is below the common mode voltage in the period (3).
<Periods (5) to (11)>
The operation which is one of the period (1) to the period (4) is repeated in the periods (5) to (11) as well.
The configuration of a logic circuit that generate, from input signals INT and INB, signals EMT and EMB which controls the pre-emphasis is well known. Various types of implementation are possible. Depending on a current bit supplied to the terminal INT and the immediately preceding bit of the current bit (held in a flip-flop), the signal EMT assumes one of the following states, for example:
if (current bit, immediately preceding bit)=(High, Low), the signal EMT is High,
if (current bit, immediately preceding bit)=(High, High), the signal EMT is Low,
if (current bit, immediately preceding bit)=(Low, High), the signal EMT is Low, and
if (current bit, immediately preceding bit)=(Low, Low), the signal EMT is High.
The signal EMB is the complementary signal of the signal EMT.
The output circuit shown in FIG. 6 does not have the function of suppressing the variation of the common mode voltage VCM. Thus, the common mode voltage (VCM) may differ between the transition bit and the de-emphasis bit. The variation of the common mode voltage VCM may increase (deteriorate). That is, without modification of the specifications such as increase of supply voltage and reduction of output amplitude, nonconformity with the specifications of the standard interface (PCI-Express/Serial-ATA/CEI) may occur. The specification for the variation of the AC common mode voltage (Vcmac) is, for example, 50 mVpp in SATA (Serial-Advanced Technology Attachment), as shown in FIG. 11.
In the output circuit conforming to the standard interface specifications, operation with the low supply voltage is demanded in order to achieve low power consumption. When the large differential output amplitude (greater than or equal to 800 mV and less than or equal to 1200 mV) of the PCI-Express interface is to be implemented with the low supply voltage in the circuit in FIG. 6, the variation of the common mode voltage (VCM) between the transition bit and the de-emphasis bit increases. When the variation of the common mode voltage VCM increases, a delay at input of a receiver circuit (differential receiver circuit) that receives the differential signals from the differential output terminals OUTT and OUTB varies. This delay variation becomes a jitter. The time interval during which the receiver circuit can receive the differential signals is reduced, thereby deteriorating jitter tolerance.
FIG. 9 is a diagram showing a configuration of a common circuit that stabilizes the common mode voltage VCM using a feedback circuit. Referring to FIG. 9, the circuit includes a driver main buffer 10′, a pre-emphasis buffer 20′, and a VCM feedback unit 21. The driver main buffer 10′ includes a PMOS transistor P1 provided between a high-potential side power supply VDD and a common connection node of one ends of load resistor elements R1 and R2 having other ends connected to drains of NMOS transistors N1 and N2. The VCM feedback unit 21 includes an operational amplifier (OPAMP) in which a center voltage COM between output terminals OUT and OUTB (voltage at a connection node of resistors R3 and R4 provided between the output terminals OUTT and OUTB) in the pre-emphasis driver 20′ is supplied to a non-inverting input, a common mode reference voltage (VCMREF) is supplied to an inverting input, and an output is connected to a gate of the PMOS transistor P1. The operational amplifier (OPAMP) controls a gate voltage of the PMOS transistor P1 and adjusts a drain voltage VD1 (voltage at a connection node of the load resistor elements R1 and R2) of the PMOS transistor P1 so that the center voltage (common mode voltage) (COM) matches with the voltage VCMREF. Feedback is thereby applied to the common mode voltage (COM). A tracking speed of the circuit in this method of stabilizing the common mode voltage VCM depends on a tracking speed of the feedback circuit including the operational amplifier (OPAMP) and the PMOS transistor P1. For this reason, the circuit in FIG. 9 is effective for the variation of the common mode voltage VCM of the order of not more than several dozen MHz. However, the circuit in FIG. 9 cannot track the variation of the common mode voltage VCM at high speed exceeding 1 GHz such as the variation of the VCM between the transition bit and the de-emphasis bit in the standard interface such as PCI-Express/Serial-ATA/CEI. The circuit in FIG. 9 cannot accommodate the high-speed variation of the common mode voltage VCM.
As shown in FIG. 4 of Patent Document 1, two PMOS transistors having drains respectively connected to the drains of the NMOS transistors N3 and N4 in the pre-emphasis buffer of the circuit in FIG. 6 are provided. Then, a third PMOS transistor is provided between coupled sources of these two PMOS transistors and a power supply VDD to compensate for a common mode variation of a de-emphasis bit. In this case, four transistors are cascoded, which is not suited to a low supply voltage. Further, the PMOS transistors are connected in parallel with the resistors R1 and R2. Thus, an output DC impedance decreases.
FIG. 10 shows a configuration of an output circuit (current mode logic driver) disclosed in Patent Document 2. FIG. 10 has been prepared, based on a configuration in FIG. 5 of Patent Document 2. Referring to FIG. 10, a driver main buffer 10 and a pre-emphasis buffer 20 are the same as those in the configuration in FIG. 6. As shown in FIG. 10, the output circuit includes a level shift mechanism. The level shift mechanism includes a current source Ipu of a VCM pull-up mechanism between a high-potential side power supply VDD and an output terminal OUTT, and a current source Ipd of a VCM pull-down mechanism between the output terminal OUTT and a low-potential side power supply VSS. The level shift mechanism includes a current source Ipu of the VCM pull-up mechanism between the high-potential side power supply VDD and an output terminal OUTB, and a current source Ipd of the VCM pull-down mechanism between the output terminal OUTB and the low-potential side power supply VSS. A resistor R3 connected between the differential output terminals OUTT and OUTB of the output circuit is a load resistor.
In the following description, it is assumed that the pre-emphasis buffer 20 is in a non-operation state (accordingly, NMOS transistors N3 and N4 are both turned OFF). It is also assumed that an NMOS transistor N1 is turned ON, and an NMOS transistor N2 is turned OFF. There are two sets of current paths I1 and I2 in the circuit, and a value of current of each current path is determined by a ratio among resistor elements R1 and R2 and the resistor element R3. In this case, the output terminal OUTT outputs a High level (VOH). This level is given by:VOH=VDD−I2×R2
On the other hand, the output terminal OUTB outputs a Low level (VOL). This level is given by:VOL=VDD−I1×R1
A common mode voltage (VCM) is expressed by:
                    VCM        =                              (                          VOH              +              VOL                        )                    /          2                                        =                  VDD          -                                    (                                                I                  ⁢                                                                          ⁢                  1                  ×                  R                  ⁢                                                                          ⁢                  1                                +                                  I                  ⁢                                                                          ⁢                  2                  ×                  R                  ⁢                                                                          ⁢                  2                                            )                        /            2                              
When the common mode voltage (VCM) is to be increased, the two constant current sources Ipu of the VCM pull-up mechanism connected between the differential output terminals (OUTT, OUTB) and the power supply VDD are both turned ON, and the two constant current sources Ipd of the VCM pull-down mechanism connected, between the differential output terminals (OUTT, OUTB) and the GND (VSS) are turned OFF.
In this case, the output High level is given by:VOH=VDD−(I2−Ipu)×R2,and the output Low level is given by:VOL=VDD−(I1−Ipu)×R1
The common mode voltage (VCM) is given by:
                    VCM        =                              (                          VOH              +              VOL                        )                    /          2                                        =                  VDD          -                                    (                                                I                  ⁢                                                                          ⁢                  1                  ×                  R                  ⁢                                                                          ⁢                  1                                +                                  I                  ⁢                                                                          ⁢                  2                  ×                  R                  ⁢                                                                          ⁢                  2                                            )                        /            2                    +                      Ipu            ×                                          (                                                      R                    ⁢                                                                                  ⁢                    1                                    +                                      R                    ⁢                                                                                  ⁢                    2                                                  )                            /              2.                                          Then, the potential of the VCM increases by an amount of Ipu×(R1+R2)/2.
When the common mode voltage (VCM) is to be lowered, the two constant current sources Ipu of the VCM pull-up mechanism connected between the differential output terminals (OUTT, OUTB) and the power supply VDD are both turned OFF, and the two constant current sources Ipd of the VCM pull-down mechanism connected between the differential output terminals (OUTT, OUTB) and the GND (VSS) are turned ON. In this case, the output High level is given by:VOH=VDD−(I2+Ipd)×R2,and the output Low level is given by:VOL=VDD−(I1+Ipd)×R1
The common mode voltage (VCM) is given by:
                    VCM        =                              (                          VOH              +              VOL                        )                    /          2                                        =                  VDD          -                                    (                                                I                  ⁢                                                                          ⁢                  1                  ×                  R                  ⁢                                                                          ⁢                  1                                +                                  I                  ⁢                                                                          ⁢                  2                  ×                  R                  ⁢                                                                          ⁢                  2                                            )                        /            2                    -                      Ipd            ×                                          (                                                      R                    ⁢                                                                                  ⁢                    1                                    +                                      R                    ⁢                                                                                  ⁢                    2                                                  )                            /              2.                                          Then, the potential of the VCM decreases by an amount of Ipd×(R1+R2)/2.
By controlling current values of the constant current sources Ipu of the VCM pull-up mechanism connected between the output terminals (OUTT, OUTB) and the power supply (VDD) and current values of the constant current sources Ipd of the VCM pull-down mechanism connected between the output terminals (OUTT, OUTB) and the GND (VSS) in this manner, the common mode voltage VCM can be adjusted.                [Patent Document 1] US2008/0001630A1        [Patent Document 2] JP Patent Kokai Publication No. JP-P-2004-350272A        